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1 ? fn9219.5 isl9011 dual ldo with low noise, low i q and high psrr isl9011 is a high performance dual ldo capable of sourcing 150ma current from channel 1 and 300ma from channel 2. the device has a low standby current and high-psrr and is stable with output capacitance of 1f to 10f with esr of up to 200m . a reference bypass pin allows an external capacitor for adjusting a noise filter for low noise and high psrr applications. the quiescent current is typically only 45a with both ldo?s enabled and active. separate enable pins control each individual ldo output. when both enable pins are low, the device is in shutdown, typically drawing less than 0.1a. several combinations of voltage outputs are standard. output voltage options for each ldo range from 1.5v to 3.3v. other output voltage options may be available upon request. pinout isl9011 (10 ld 3x3 dfn) top view features ? integrates two high performance ldos - vo1 - 150ma output - vo2 - 300ma output ? excellent transient response to large current steps ? excellent load regulation: <1% voltage change across full range of load current ? high psrr: 70db @ 1khz ? wide input voltage capability: 2.3v to 6.5v ? extremely low quiescent curr ent: 45a (both ldos active) ? low dropout voltage: typically 120mv @ 150ma ? low output noise: typically 30v rms @ 100a (1.5v) ? stable with 1f to10f ceramic capacitors ? separate enable pins for each ldo ? soft-start to limit input current surge during enable ? current limit and overheat protection ? 1.8% accuracy over all operating conditions ? tiny 10 ld 3mmx3mm dfn package ? -40c to +85c operating temperature range ? pin compatible with micrel mic2211 ? pb-free (rohs compliant) applications ? pdas, cell phones and smart phones ? portable instruments, mp3 players ? handheld devices including medical handhelds vin en1 en2 cbyp nc vo1 vo2 nc nc gnd 2 3 4 1 5 9 8 7 10 6 data sheet march 10, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2005, 2006, 2008. all rights reserved. all other trademarks mentioned are the property of their respective owners. n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t i s l 901 1a
2 fn9219.5 march 10, 2008 ordering information part number (notes 1, 2, 3) part marking vo1 voltage (v) vo2 voltage (v) temp range (c) package (pb-free) pkg. dwg. # isl9011irnnz daam 3.3 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irnjz dtaa 3.3 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irnfz dvaa 3.3 2.5 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irncz daan 3.3 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irmnz daap 3.0 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irmmz dana 3.0 3.0 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irmgz daas 3.0 2.7 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irllz dama 2.9 2.9 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irknz daaw 2.85 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irkkz dwaa 2.85 2.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irkjz dyaa 2.85 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irkfz daba 2.85 2.5 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irkpz ddha 2.85 1.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irkcz daea 2.85 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irjnz daay 2.8 3.3 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irjmz dala 2.8 3.0 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irjrz daka 2.8 2.6 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irjcz daja 2.8 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irjbz daca 2.8 1.5 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irgpz ddga 2.7 1.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irgcz daha 2.7 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irfjz dada 2.5 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irfdz dcra 2.5 2.0 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irfcz dbma 2.5 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irplz daga 1.85 2.9 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irppz ddda 1.85 1.85 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011ircjz dbva 1.8 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irccz dcsa 1.8 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irblz dbbf 1.5 2.9 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irbjz dafa 1.5 2.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irbcz dbbh 1.5 1.8 -40 to +85 10 ld 3x3 dfn l10.3x3c isl9011irbbz ddea 1.5 1.5 -40 to +85 10 ld 3x3 dfn l10.3x3c notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. for availability and lead time of device s with voltage combinations not listed in the table, contact intersil marketing. 3. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering oper ations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. isl9011
3 fn9219.5 march 10, 2008 absolute maximum rati ngs thermal information supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1v v o 1, v o 2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v in + 0.3)v recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . .-40c to +85c supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 6.5v thermal resistance (notes 4, 5) ja (c/w) jc (c/w) 10 ld 3x3 dfn package . . . . . . . . . . . 50 10 junction temperature range . . . . . . . . . . . . . . . . .-40c to +125c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameters are guaranteed ov er the operational supply voltage and temperature range of the device as follows: t a = -40c to +85c; v in = (v o + 1.0v) to 6.5v with a minimum v in of 2.3v; c in = 1f; c o = 1f; c byp =0.01f: parameter symbol test conditions min (note 7) typ max (note 7) units dc characteristics supply voltage v in 2.3 6.5 v ground current quiescent condition: i o1 = 0a; i o2 = 0a i dd1 one ldo active 25 40 a i dd2 both ldo active 45 60 a shutdown current i dds @ +25c 0.1 1.0 a uvlo threshold v uv+ 1.9 2.1 2.3 v v uv- 1.6 1.8 2.0 v regulation voltage accuracy variation from nominal voltage output, v in = v o + 0.5v to 5.5v, t j = -40c to +125c -1.8 +1.8 % line regulation v in = (v out + 1.0v relative to highest output voltage) to 5.5v -0.2 0 0.2 %/v load regulation i out = 100a to 150ma (vo1 and vo2) 0.1 0.7 % i out = 100a to 300ma (vo2) 1.0 % maximum output current i max vo1: continuous 150 ma vo2: continuous 300 ma internal current limit i lim 350 475 600 ma dropout voltage (note 6) v do1 i o = 150ma; v o > 2.1v (vo1) 125 200 mv v do2 i o = 300ma; v o < 2.5v (vo2) 300 500 mv v do3 i o = 300ma; 2.5v v o 2.8v (vo2) 250 400 mv v do4 i o = 300ma; v o > 2.8v (vo2) 200 325 mv thermal shutdown temperature t sd+ 145 c t sd- 110 c ac characteristics ripple rejection i o = 10ma, v in = 2.8v(min), v o = 1.8v, c byp = 0.1f @ 1khz 70 db @ 10khz 55 db @ 100khz 40 db output noise voltage i o = 100a, v o = 1.5v, t a = +25c, c byp = 0.1f bw = 10hz to 100khz 30 v rms isl9011
4 fn9219.5 march 10, 2008 device start-up characteristics device enable time t en time from assertion of the enx pin to when the output voltage reaches 95% of the vo(nom) 250 500 s ldo soft-start ramp rate t ssr slope of linear portion of ldo output voltage ramp during start-up 30 60 s/v en1, en2 pin characteristics input low voltage v il -0.3 0.5 v input high voltage v ih 1.4 v in + 0.3 v input leakage current i il , i ih 0.1 a pin capacitance c pin informative 5 pf note: 6. vox = 0.98*vox(nom); valid for vox greater than 1.85v. 7. parts are 100% tested at +25c. temperature limits es tablished by characterization and are not production tested. electrical specifications unless otherwise noted, all parameters are guaranteed ov er the operational supply voltage and temperature range of the device as follows: t a = -40c to +85c; v in = (v o + 1.0v) to 6.5v with a minimum v in of 2.3v; c in = 1f; c o = 1f; c byp =0.01f: (continued) parameter symbol test conditions min (note 7) typ max (note 7) units isl9011
5 fn9219.5 march 10, 2008 typical performance curves figure 1. output voltage vs input voltage (3.3v output) figure 2. output voltage change vs load current figure 3. output voltage change vs temperature figure 4. output voltage vs input voltage (vo1 = 3.3v) figure 5. output voltage vs input voltage (vo2 = 2.8v) figure 6. dropout voltage vs load current output voltage, vo (%) input voltage (v) -0.6 -0.2 0.2 0.6 -0.8 3.8 4.2 6.2 5.8 6.6 3.4 4.6 5.0 5.4 -0.4 0.0 0.4 0.8 vo = 3.3v +85c -40c +25c i load = 0ma 0.04 0.06 -0.06 -0.10 100 200 300 400 0 load current - i o (ma) output voltage change (%) -0.02 0.00 0.02 0.08 0.10 -0.04 -0.08 50 150 250 350 vin = 3.8v vo = 3.3v +85c -40c +25c 0.04 0.06 -0.06 -0.10 -10 20 50 110 -40 temperature (c) output voltage change (%) -0.02 0.00 0.02 0.08 0.10 -0.04 -0.08 -25 5 35 80 65 95 125 vin = 3.8v vo = 3.3v i load = 0ma output voltage, vo (v) input voltage (v) 3.0 3.1 3.2 3.3 3.4 2.9 2.8 3.1 3.6 4.1 4.6 5.1 6.1 5.6 i o = 150ma i o = 0ma vo1 = 3.3v 6.5 2.5 2.6 2.7 2.8 2.9 2.4 2.3 2.63.13.64.14.65.1 6.1 input voltage (v) output voltage, vo (v) 5.6 i o = 0ma i o = 300ma vo2 = 2.8v i o = 150ma 6.5 200 250 300 350 150 100 50 0 50 100 150 200 250 300 350 400 0 output load (ma) dropout voltage, v do (mv) vo2 = 2.8v vo1 = 3.3v isl9011
6 fn9219.5 march 10, 2008 figure 7. vo1 dropout voltage vs load current figure 8. ground current vs input voltage figure 9. ground current vs load figure 10. ground current vs temperature figure 11. power-up/power-down figure 12. turn-on/turn-off response typical performance curves (continued) 100 125 150 175 75 50 25 0 25 50 75 100 125 150 175 200 0 output load (ma) dropout voltage, v do (mv) vo1 = 3.3v +85c +25c -40c 30 35 40 45 55 25 4.0 5.0 6.5 input voltage (v) ground current (a) 50 3.0 3.5 4.58 5.5 6.0 i o (both channels) = 0a vo1 = 3.3v vo2 = 2.8v -40c +25c +125c 200 160 100 20 0 50 100 150 200 250 400 0 load current (ma) ground current (a) 350 300 vo1 = 3.3v vin = 3.8v vo2 = 2.8v 40 60 80 120 140 180 +85c -40c +25c 35 25 -10 20 50 110 -40 temperature (c) ground current (a) 45 50 55 40 30 -25 5 35 80 65 95 125 vin = 3.8v vo = 3.3v i load = 0a both outputs on 2 3 4 5 1 0 1234567 10 time (s) voltage (v) 89 vo2 vo1 vin 0 vo1 = 3.3v vo2 = 2.8v i l 1 = 150ma i l 2 = 300ma 1 3 0 2 0 100 200 300 400 500 600 700 800 0 time (s) vo1 (v) ven (v) 5 vo1 = 3.3v vin = 5.0v i l 1 = 150ma c l -1, c l -2 = 1f c byp = 0.01f 900 1000 vo2 (10mv/div) i l 2 = 300ma vo2 = 2.8v isl9011
7 fn9219.5 march 10, 2008 figure 13. line transient response, 3.3v output figure 14. line transient response, 2.8v output figure 15. load transient response figure 16. psrr vs frequency figure 17. spectral noise density vs frequency typical performance curves (continued) 400 s/div vo1 = 3.3v i load = 150ma 3.6v 4.3v 10mv/div c load = 1f c byp = 0.01f 400s/div vo2 = 2.8v i load = 300ma 3.5v 4.2v 10mv/div c load = 1f c byp = 0.01f 100s/div vo (25mv/div) i load 300ma 100a vin = 2.8v vo = 1.8v 0.1 1k 10k 100k 1m frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 psrr (db) vin = 3.6v vo = 1.8v i o = 10ma c byp = 0.1f c load = 1f spectral noise density (nv/ hz ) 1000 100 10 1 0.1 10 100 1k 10k 100k 1m frequency (hz) vin = 3.6v vo = 1.8v i load = 10ma c byp = 0.1f c in = 1f c load = 1f isl9011
8 fn9219.5 march 10, 2008 pin description typical application pin number pin name type description 1 vin analog i/o supply voltage/ldo input: connect a 1f capacitor to gnd. 2 en1 low voltage compatible cmos input ldo-1 enable. 3 en2 low voltage compatible cmos input ldo-2 enable. 4 cbyp analog i/o reference bypass capacitor pin: optionally connect capacitor with a value of 0. 01f to 1f between this pin and gnd to tune in the desired noise and psrr performance. 5, 7, 8 nc nc no connection 6 gnd ground gnd is the connection to syst em ground. connect to pcb ground plane. 9vo2 analog i/o ldo-2 output: connect capacitor with a value of 1f to 10f to gnd (1f recommended). 10 vo1 analog i/o ldo-1 output: connect capacitor with a value of 1f to 10f to gnd (1f recommended). c1, c3, c4: 1 f x5r ceramic capacitor c2: 0.1 f x5r ceramic capacitor isl9011 vin en1 en2 cbyp nc vo1 vo2 nc nc gnd 10 9 8 7 6 1 2 3 4 5 vin (2.3 to 6.5v) enable1 enable2 vout 1 vout 2 c1 c2 c3 c4 off on off on isl9011
9 fn9219.5 march 10, 2008 block diagram functional description the isl9011 contains all circuitry required to implement two high performance ldo?s. high performance is achieved through a circuit that deliver s fast transient response to varying load conditions. in a quiescent condition, the isl9011 adjusts its biasing to achieve the lowest standby current consumption. the device also integrates cu rrent limit protection, smart thermal shutdown protection, st aged turn-on and soft-start. smart thermal shutdown protects the device against overheating. staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. power control the isl9011 has two separate enable pins (en1 and en2) to individually control power to each of the ldo outputs. when both en1 and en2 are low, the device is in shutdown mode. during this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1a. when one or both of the enable pins are asserted, the device first polls the output of the uvlo detector to ensure that vin voltage is at least about 2.1v. once verified, the device initiates a start-up sequence. during the start-up sequence, trim settings are first read and latched. then, sequentially, the bandgap, re ference voltage and current generation circuitry power-up. once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the cbyp pin) to the proper operating voltage. after the bypass capacitor has been charged, the ldo?s power-up. if en1 is brought high, and en2 goes high before the vo1 output stabilizes, the isl9011 delays the vo2 turn-on until the vo1 output reaches its target level. ldo error amplifier is1 1v qen1 ldo-1 ldo-2 vref trim vin vo1 vo2 cbyp gnd en2 en1 control logic voltage reference generator bandgap and temperature sensor uvlo 1.00v is1 is2 qen1 qen2 vo1 ~1.0v isl9011
10 fn9219.5 march 10, 2008 if en2 is brought high, and en1 goes high before vo2 starts its output ramp, then vo1 turns on first and the isl9011 delays the vo2 turn-on until the vo1 output reaches its target level. if en2 is brought high, and en1 goes high after vo2 starts its output ramp, then the isl9011 immediately starts to ramp up the vo1 output. if both en1 and en2 are brought high at the same time, the vo1 output has priority, and is always powered up first. during operation, whenever the vin voltage drops below about 1.8v, the isl9011 immediately disables both ldo outputs. when vin rises back above 2.1v, the device re-initiates its start-up sequence and ldo operation will resume automatically. reference generation the reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an rc noise filt er. the filter includes the external capacito r connected to the cbyp pin. a 0.01f capacitor connected cbyp implements a 100hz lowpass filter, and is recommended for most high performance applications. for the lowest noise application, a 0.1f or greater cbyp capacitor should be used. this filters the reference noise to below the 10hz to 1khz frequency band, which is crucial in many noise-sensitive applications. the bandgap generates a zero te mperature coefficient (tc) voltage for the reference divider. the reference divider provides the regulation reference and other voltage references required for current generation and over-temperature detection. the current generator outputs references required for adaptive biasing as well as references for ldo output current limit and therma l shutdown determination. ldo regulation and programmable output divider the ldo regulator is implemented with a high-gain operational amplifier driving a pmos pass transistor. the design of the isl9011 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. ldo stability is guaranteed for a 1f to 10f output capacitor that has a tolerance better than 20% and esr less than 200m . the design is performance-optimized for a 1f capacitor. unless limited by the application, use of an output capacitor value above 4.7f is not recommended as ldo performance improvement is minimal. soft-start circuitry integrated into each ldo limits the initial ramp-up rate to about 30s/v to minimize current surge. the isl9011 provides short-circuit protection by limiting the output current to about 475ma. each ldo uses an independently trimmed 1v reference. an internal resistor divider drops the ldo output voltage down to 1v. this is compared to the 1v reference for regulation. the resistor division ratio is programmed in the factory. overheat detection the bandgap outputs a proporti onal-to-temperature current that is indicative of the temp erature of the silicon. this current is compared with references to determine if the device is in danger of damage due to overheating. when the die temperature reaches about +145c, one or both of the ldo?s momentarily shut down until the die cools sufficiently. in the overheat condition, only the ldo sourcing more than 50ma will be shut off. this do es not affect the operation of the other ldo. if both ldos source more than 50ma and an overheat condition occurs, both ldo outputs are disabled. once the die temperature falls back below about +110c, the disabled ldo(s) are re-enabled and soft-start automatically takes place. isl9011
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9219.5 march 10, 2008 isl9011 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k 9 l m l10.3x3c 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.85 0.90 0.95 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 3.00 bsc - d2 2.33 2.38 2.43 7, 8 e 3.00 bsc - e2 1.59 1.64 1.69 7, 8 e 0.50 bsc - k0.20 - - - l 0.35 0.40 0.45 8 n102 nd 5 3 rev. 1 4/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for dimensions e2 & d2.

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